论文总字数：28010字

摘 要

当下，生产生活中产生的数量呈爆发式增长，对大带宽、高速率数字通道的需求急剧增长。数据分接器作为数字通道中的关键功能模块之一，国内外对高速率、低功耗分接器的研究一直在进行。随着工艺的不断发展，CMOS器件的截至频率不断提高，基于CMOS逻辑风格的高速分接器电路的研究成果不断涌现。

课题在0.5m CSMC工艺条件下实现工作速率为100Mbps的1：4DMUX电路设计。该电路采用半速率树型结构，由两级1：2 DMUX电路、2分频器和时钟输入缓冲电路构成。其中，1：2DMUX电路由5个静态D锁存器构成，2分频功能由D锁存器构成的T触发器实现，时钟输入缓冲电路由采用倒向器正反馈结构的倒向器链构成，实现一定的延时和差分时钟信号输出的功能。电路设计选用当下高速电路设计中流行的CMOS逻辑风格，有利于降低电路功耗和芯片面积，便于大规模生产。而且，CMOS电路拥有优越抗干扰能力，可实现与后续模块的直接耦合。

本分接器在cadence平台上进行原理图的绘制与仿真。电源电压为3.3V，电源波动10%。输入为一路100Mbps数据信号，输出为4路25Mbps数据信号。在不同温度、工艺角下条件下，电路逻辑功能验证通过且失真度小。电路设计综合速度与功耗的要求，考虑到各种不同的外部条件，最终，所设计的1：4DMUX电路的逻辑与指标满足课题要求。

关键词：分接器，CMOS，低功耗

Abstract

At present, the quantity produced in production and life has grown exponentially, and the demand for large-bandwidth, high-rate digital channels has increased dramatically. As one of the key functional modules in the digital channel, the data tapper has been researching on high-rate and low-power taps at home and abroad. With the continuous development of the technology, the cut-off frequency of CMOS devices has been continuously improved, and the research results of high-speed demux circuits based on CMOS logic styles continue to emerge.
Under the condition of 0.5μm CSMC process, a 1:4DMUX circuit design with 100Mbps operating speed is realized. The system uses a half-rate tree structure and consists of a two-stage 1:2 DMUX circuit, a two-divider, and a clock input buffer circuit. Among them, 1:2 DMUX circuit is made up of 5 static D latches, 2 frequency division function is realized by T flip-flops that D latches form, the clock input buffer circuit is made up of the chain of reversers that adopts the positive feedback structure of the reversing device , to achieve a certain delay and differential clock signal output function. The system design selects the popular CMOS logic style in the current high-speed circuit design, which helps to reduce the circuit power consumption and chip area, and facilitates large-scale production. Moreover, the CMOS circuit has superior anti-interference ability and can realize direct coupling with subsequent modules.

The tapper draws and simulates the schematic diagram on the cadence platform. The power supply voltage is 3.3V and the power supply is fluctuating by 10%. The input is a 100Mbps data signal and the output is 4 25Mbps data signals. Under different temperature and process angle conditions, the circuit logic function is verified and the distortion is small. The requirements of the integrated speed and power consumption of the chip design take into account various external conditions. In the end, the logic and indicators of the designed 1:4 DMUX circuit meet the requirements of the project.

KEY WORDS: DMUX, CMOS, low power consumption

目 录

摘要 I

Abstract II

目录 III

第一章 绪论 1

1.1 研究背景 1

1.2 国内外研究现状 1

1.3 论文研究内容 2

1.4 论文研究难点 2

1.5 论文组织结构 3

第二章 1：4DMUX设计原理 5

2.1 数据分接原理 5

2.2 分接器的基本结构 6

2.2.1 串型分接器 6

2.2.2 并型分接器 7

2.2.3 树型分接器 7

2.3 CMOS电路基本原理 8

2.3.1 扇入与扇出 9

2.3.2 衬底偏置效应 10

2.3.3 输出单元 11

2.4 本章小结 11

第三章 1：4DMUX电路设计 12

3.1 1：4DMUX设计说明 12

3.2 1：4DMUX总体电路结构图 12

3.3 1：4DMUX设计难点分析 12

3.4 本章小结 15

第四章 1：4DMUX基本单元设计 16

4.1 倒向器 16

4.1.1 倒向器的静态特性分析 17

4.1.2 倒向器的动态特性分析 17

4.1.3 延时和延时功耗积分析 18

4.2 传输门 19

4.3 静态D锁存器 19

4.4 本章小结 20

第五章 1：4DMUX模块电路设计与仿真 21

5.1 1：2DMUX设计 21

5.2 时钟分频器 21

5.3 时钟输入缓冲电路 22

5.4 数据输出缓冲电路 22

5.5 综合电路仿真 23

5.5.1 理想状态下仿真结果 24

5.5.2 非理想状态下仿真结果 26

5.6 本章小结 26

第六章 总结与展望 27

6.1 总结 27

6.2 展望 27

致谢 28

参考文献 29

附录A 30

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