电力开关设备在线监测系统硬件设计

论文总字数：26335字

摘 要

本文介绍了为满足电力开关在线监测而设计的下位机方案，该方案下位机系统的基本思想是：利用FPGA的时序控制能力实现多路信号的高精度，高速的采样，利用ARM的网络通信能力实现监测数据的以太网传输。

为完成方案要求，本文进行了FPGA内部与ARM接口相关部分的硬件电路设计。通过分析ARM和FPGA内部时序的差异,针对ARM与FPGA内部FIFO时序不匹配的问题,解决了测量高压电力开关采集与处理速度不匹配的问题。再来就是完成ARM以太网通信最小系统的设计，以完成下位机与上位机高速稳定的数据传递。

关键词：电力开关；在线监测；ARM；FPGA；以太网通信

Power switching equipment on-line monitoring system hardware design

Abstract

This paper introduces the designed to meet the power switch online monitoring of lower computer. The basic idea of this lower computer system is: use the FPGA timing control to achieve high precision of multichannel signal, high speed sampling, and use the ability of ARM’s network communication to realization the Ethernet monitoring data transmission. In order to complete the program, this paper designed hardware circuit – internal of the FPGA and some parts of the ARM interface. By analyzing the difference of internal timing and contrary to the problem of FIFO timing mismatch between ARM and FPGA, to resolved the problem of mismatch between the measurement of high voltage circuit breaker acquisition and processing speed. Additionally, to complete the smallest design of ARM Ethernet communication system, in order to achieve the high-speed stable data transfer between lower computer and upper computer.

Keywords: power switch; on-line monitoring; ARM; FPGA; Ethernet communication

目录

摘要···············································································I

Abstract············································································II

目录···············································································III

第一章 引言·········································································1

1.1 设计背景·······································································1

1.2 电力开关监测的研究进程和现状···················································1

1.2.1 发展历史·····································································1

1.2.2 研究现状·····································································2

1.3 本文内容·······································································2

第二章 基于ARM和FPGA的系统的总体设计············································4

2.1 系统总体架构···································································4

2.2 背景技术介绍···································································5

2.2.1 电力开关概述·································································5

2.2.2 A/D转换芯片··································································6

2.2.3FPGA概述····································································6

2.2.4 ARM概述····································································6

2.3芯片的选择使用··································································7

第三章 FPGA和ARM的硬件电路设计··················································8

3.1 设计工具·······································································8

3.1.1 Quartus II和Verilog语言·························································8

3.1.2 ADS和C语言·································································9

3.2 FPGA电路设计··································································9

3.2.1 总体设计·····································································9

3.2.2 baundgeneration模块···························································10

3.2.3ADS8365模块································································11

3.2.4 fpga send模块································································14

3.3 ARM的硬件电路设计····························································18

第四章 ARM程序和运行结果·························································21

4.1 ARM通信程序的实现····························································21

4.2系统运行测试···································································26

4.2.1 测试程序····································································26

4.2.2 测试结果····································································26

第五章 结束语······································································28

参考文献···········································································29

致谢···············································································30

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