5GHz低电压低功耗CMOS双模分频器设计

论文总字数：27288字

摘 要

本课题来源于国家自然科学基金面上项目“低功耗射频收发技术研究”。该项目基于0.18μm RF-CMOS工艺，主要由高速二分频器和8/9双模预分频器组成。

本文首先介绍了几种典型的模拟分频器和数字分频器的电路结构、工作原理以及各自的优点、不足。进而通过分析双模分频器的设计指标，选择合适的结构分别实现高速二分频器和双模8/9分频器的功能，以达到16/18分频的效果。之后详细介绍了各模块的工作原理。

考虑到本次设计中要求低功耗，而电压也较低只有1V，因此高速二分频器采用伪差分触发器结构来实现；8/9双模预分频器则采用同步2/3分频器和异步4分频器级联而成，其中，同步2/3分频器采用了SCL伪差分结构（改变时钟输入管的位置并集成或门）而异步4分频器采用了一种改进的TSPC结构实现。

整个双模16/18分频器采用0.18μm CMOS工艺设计，前仿真结果表明：在1V电源电压，各工艺角温度组合下电路均能准确实现16/18分频，工作频率范围为4.6-5.2GHz，总的工作电流约为611.8μA，满足指标要求。

关键词：低电压，低功耗，高速二分频器，双模预分频器，伪差分结构，TSPC

结构

DESIGN OF LOW VOLTAGE DUAL-MODULUS PRESCALER OF THE FRACTIONAL PLL-BASED FREQUENCY SYNTHESIZER IN WSN

Abstract

This topic is derived from the national natural science fund project “low power consumption RF transceiver technology research”. The project is based on 0.18 mu RF-CMOS M technology, for wireless sensor networks (WSN) RF transceiver chip, mainly includes a high-speed divider by 2 and a dual-modulus prescaler(DMP).

Firstly, several typical analog and digital frequency divider structures are introduced in the paper, then the working principles of these structure and their advantages and disadvantages are analyzed respectively. Then, the paper analyzes the design indexes of the dual-modulus frequency divider and selects the appropriate structure for the divider by 2 and DMP.

As the main design target of the design is low voltage and low power consumption, the high-speed divider by 2 adopts the pseudo-differential structure. The DMP with division ratio 8/9 is divided into a synchronous DMP with division ration 2/3 and an asynchronous divider by 4, and the synchronous division ration 2/3 adopts the pseudo-differential structure(the position of the clock input transistor is changed and the OR gate is integrated in the structure) and asynchronous dividers by 2 are realized by an improved TSPC structure.

The whole frequency divider is simulated in 0.18μm CMOS process. The simulation results show that under the voltage supply of 1V , the frequency divider can work accurately with division ratio 16/18 under all kind of process corner and temperature combination, and the operating frequency range is 4.6~5.2GHz. The total supply current is about 611.8μA, which meets the requirements of the system indexes.

KEY WORDS: Low Voltage, Low Power Consumption, High-Speed Divider by 2, Dual-Modulus Prescaler, Pseudo-Differential Structure, TSPC Structure

目 录

摘要

Abstract

第一章 绪 论

1.1 引言

1.2 双模分频器研究现状 1

1.3 设计内容与设计指标 3

1.4 论文组织 3

第二章 分频器结构 4

2.1 模拟分频器 4

2.1.1 再生式分频器（RFD） 5

2.1.2 注入锁定分频器（ILFD） 5

2.2 数字分频器 7

2.2.1 源级耦合逻辑触发器 7

2.2.2 伪差分结构触发器 9

2.2.3 平行电流开关结构触发器 10

2.2.4 钟控CMOS触发器 11

2.2.5 真单相时钟触发器 11

2.3 小结 13

第三章 小数分频锁相环中的二分频器的设计 13

3.1 高速二分频器核心电路 14

3.2 高速二分频器前仿真 16

第四章 小数分频锁相环中的双模8/9分频器的设计 19

4.1 双模8/9分频器结构选择 19

4.2 同步2/3分频器的设计 22

4.3 缓冲电路的设计 24

4.4 异步4分频器的设计 26

4.5 反相器 28

4.6 互补CMOS逻辑门设计 28

4.7 双模16/18分频器前仿真 30

小结 36

第五章 总结与展望 37

致谢 38

参考文献(References) 39

1. 绪 论

1.1 引言

无线传感器网络(WSN)是通过无线通讯的方法，利用传感器节点感知并采集被观察对象的信息，进行处理后送给观察者，将这些或静止或移动的微型传感器节点连接起来构成的网络就称为无线传感网，这些节点之间没有确定的传输路径，具有自组织多跳等特点。由于这些传感器节点体积小，数量庞大，因此WSN系统一般采用电池供电，而为了使其能够持久有效，要求该系统功耗越低越好。

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