基于FPGA的AES对称加密算法的实现

论文总字数：29359字

摘 要

在互联网快速发展的当下，社会对信息安全的依赖日益增强，确保数据安全在任何领域都表现出极高的重要性，尤其是在政治、商业、国防等方向。因此，能够保护信息安全，防止信息被窃取的密码学就显得举足轻重。由于黑客技术也获得了巨大的发展，因此密码学逐渐成为信息技术的重要领域，对加密算法的研究就显得尤为重要。随着对密码学研究的不断深入， NIST公开征集了新一代数据加密标准，即AES高级加密标准，经过筛选，最终将Rijndael算法作为最终的AES算法。加密算法设计的首要需求就是安全性，其次是效率和灵活性，Rijndael算法在候选算法中更胜一筹。AES算法以其免疫现有任何攻击方式、可并行处理数据、灵活性高、拥有更高的运算效率以及支持128位、192位及256位密钥等优势成为最新的国际加密标准，因此研究AES算法在硬件电路上的实现便有更大的学术意义和实用价值。

本文对AES算法的结构和实现思想进行深入研究，并对该系统的各个子模块进行优化，提高了算法的运算效率。本系统使用Verilog HDL硬件描述语言进行代码的编写，通过Quartus Ⅱ软件和FPGA器件进行验证与仿真，得到具有AES算法加密功能的设计，并进行性能分析。采用软硬件相结合的方式，提高算法的安全性和灵活性，在速度和资源占用方面具有一定的优势。

关键词：AES；FPGA；Quartus Ⅱ；信息安全

Implementation of AES symmetric encryption algorithm based on FPGA

Abstract

With the rapid development of the Internet, the society is increasingly dependent on information security. Ensuring data security is of great importance in any field, especially in politics, commerce, national defense and other directions. Therefore, cryptography, which can protect information security and prevent information from being stolen, is very important. Due to the great development of hacker technology, cryptography has gradually become an important field of information technology, so the research of encryption algorithm is particularly important. With the deepening of cryptography research, NIST has publicly recruited a new generation of data encryption standard, namely AES advanced encryption standard. After screening, Rijndael algorithm is finally used as the final AES algorithm. The primary requirement of encryption algorithm design is security, followed by efficiency and flexibility. Rijndael algorithm is better than other candidate algorithms. AES algorithm becomes the latest international encryption standard because it is immune to any existing attacks, can process data in parallel, has high flexibility, has higher operation efficiency and supports 128 bit, 192 bit and 256 bit keys. Therefore, it is of great academic significance and practical value to study the implementation of AES algorithm in hardware circuit.

In this paper, the structure and implementation of AES algorithm are deeply studied, and the sub modules of the system are optimized to improve the efficiency of the algorithm. The system uses Verilog HDL hardware description language to write the code, through the verification and Simulation of Quartus II software and FPGA devices, the design with AES algorithm encryption function is obtained, and the performance is analyzed. The combination of software and hardware can improve the security and flexibility of the algorithm, which has certain advantages in speed and resource occupation.

Keywords: AES; FPGA; Quartus Ⅱ; Information safety

目 录

摘 要 I

Abstract II

第一章 引 言 1

1.1 研究背景及其意义 1

1.1.1 数据加密算法发展历程 1

1.1.2 AES算法产生背景 1

1.2 AES算法的实现 2

1.2.1 工作模式 2

1.2.2 实现方式 3

1.3 本文研究的主要内容和结构安排 3

第二章 高级加密标准AES算法 4

2.1 算法所需的数学知识 4

2.1.1 有限域 4

2.1.2 基本运算 4

2.2 算法基本结构 4

2.2.1 字节替换 4

2.2.2 行移位 5

2.2.3 列混淆 5

2.2.4 轮密钥加 5

2.3 本章小结 6

第三章 AES算法的整体设计 7

3.1 加密模块结构设计 7

3.2 字节替换模块设计 7

3.3 轮密钥加模块设计 8

3.4 扩展密钥模块设计 8

3.5 列异或Rcon模块设计 9

第四章 AES算法的系统仿真及验证 11

4.1 Quartus Ⅱ简介 11

4.2 AES仿真 12

4.2.1 AES加密算法的功能仿真 12

4.2.2 加密算法仿真结果 12

4.3 性能分析 14

4.3.1 资源占用 14

4.3.2 功耗 14

4.4 本章小结 15

第五章 总结与展望 16

致 谢 17

参考文献 18

附 录 19

第一章 引 言

1.1 研究背景及其意义

1.1.1 数据加密算法发展历程

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