基于BiCMOS工艺的高精度LDO线性稳压器的设计

论文总字数：26594字

摘 要

电源管理类芯片飞速发展，离不开当代集成电路的快速发展，而电源管理类芯片中，低压差线性稳压器（Low-dropout Linear Regulators，LDO）由于有诸多优点，而受到了广泛的关注。包括结构十分简单，稳定性易于保证、电源电压抑制比相对较高、功耗相对低和面积相对小等，越来越广泛地运用于移动设备。

本文主要设计了一个低压差线性稳压器电路，本文用于频率综合器电路，同时也可以应用于其他各种射频电路中。LDO包括误差放大器、功率级电路、电压基准源和使能模块。首先介绍了LDO的基本结构和原理，以及LDO的一些关键指标，并且分析了指标之间的关系以及如何调整各项指标。之后分析了LDO的稳定性，介绍了环路稳定的具体定义，并且给出了让环路稳定的补偿方法，主要是密勒补偿。之后分别介绍了各个模块，其中误差放大器是最重要的模块，使用折叠式共源共栅结构，相比传统的套筒式结构，有输入输出可以短接，输入共模电平更容易选取等优点，并且输出增益更大。电压基准源采用传统的带隙基准源结构。

最后对电路进行仿真，结果显示：输入3.3V，输出1.8V的情况下，负载30mA电流时，输出电压下降0.167%，效率达到50%，开环增益93dB，能够在不同温度、器件环境、负载条件下达到稳定，带宽内电源电压抑制比50dB，线性调整率0.0082%，负载调整率0.0462%，噪声0.1599μV/@10kHz。

关键词：LDO，带隙基准源，电源电压抑制比（PSRR），折叠式共源共栅结构

ABSTRACT

The rapid development of power management chips is inseparable from the rapid development of modern integrated circuits. In power management chips, Low-dropout Linear Regulators (LDOs) have received extensive attention due to their many advantages. The advantages of LDO include simple structure, easy stability, relatively high power supply voltage rejection ratio, relatively low power consumption, and relatively small area, which are increasingly used in mobile devices.

This paper mainly designs a low-dropout linear regulator circuit, which is used in frequency synthesizer circuit and can also be applied to other various RF circuits. The LDO includes an error amplifier, a power stage circuit, a voltage reference source, and an enable module.First of all, this paper introduces the basic structure and principle of LDO, as well as some key indicators of LDO, and analyzes the relationship between indicators and how to adjust various indicators. After that, this paper analyzes the stability of LDO, introduces the specific definition of loop stability, and gives the compensation method, mainly Miller compensation. After that, the paper introduces each module separately. The error amplifier is the most important module. It uses the folded cascode structure. Compared with the traditional sleeve structure, the input and output can be shorted, and the input common mode level is easier to select. And so on, and the output gain is greater. The voltage reference uses a traditional bandgap reference structure.

Finally, this paper simulates the circuit. The final simulation results show that when the input is 3.3V, the output is 1.8V and the load is 30mA, the output vlotage drops by 0.1%, the efficiency reaches 50%, the open-loop gain is 93dB, and the stability can be obtained at different temperatures, device environments. The power supply voltage rejection ratio in the bandwidth is 50dB, the linear adjustment rate is 0.0082%, the load regulation rate is 0.0462%, and the output noise is 0.1599μV/Hz^0.5@10kHz.

KEY WORDS：LDO, Bandgap Reference, Power Supply Rejection Ratio(PSRR), Folded Cascode Structure

目 录

摘要.................................................................................................................................Ⅰ

Abstract..........................................................................................................................Ⅱ

第一章 绪论 1

1.1 课题意义及背景 1

1.2 低压差线性稳压器 2

1.3 工艺介绍 3

1.4 论文的内容和安排 4

第二章 低压差线性稳压器工作机理 5

2.1 LDO的工作机理 5

2.2 LDO的主要参数 6

2.3 LDO的稳定性分析 9

2.4 本章小结 13

第三章 LDO原理图设计及前端仿真 14

3.1 设计需求及指标 14

3.2 LDO各个基础模块设计 14

3.3 LDO的前端仿真 20

3.4 本章小结 24

第四章 LDO版图设计及后端仿真 25

4.1 LDO版图 25

4.2 LDO的后端仿真 26

4.3 本章小结 29

第五章 总结与展望 30

5.1 本次工作总结 30

5.2 未来工作展望 30

参考文献 32

致谢 34

1. 绪论
   1. 课题意义及背景

二十一世纪以来，随着科技的快速发展，电子设备的技术也不断革新，其中便携式移动电子设备的发展速度尤其快，到如今，市面上的各式各样的移动设备越来越多，比如智能手机、平板电脑、笔记本电脑等等，其功能越来越多样化。对于移动设备来说，电源能否长时间使用是至关重要的，而电源管理类芯片（Power Management Unit, PMU）则是解决该问题的关键。所以许多企业投入大量研发成本，国家大力扶持，使得电源管理类芯片得到长足的发展。

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