论文总字数：35018字

摘 要

近年来，具有高速率数据传输能力的宽带技术备受瞩目。如今，无线通信技术的发展日渐迅猛，信息传输对带宽及增益的要求与日俱增，因此迫切需要更高性能的无线通信系统。低噪声放大器是无线通信系统的接收机模块中的重要耗能部分，因此对接收机的性能影响极大。这就要求设计出工作频带更宽、增益更大、噪声更低、稳定性更好的低噪声放大器。因此，研究宽带低功耗LNA具有很好的应用价值和前景。

本文设计了一种基于TSMC 40nm CMOS工艺，工作频率覆盖为0.2~2.5GHz的低功耗低噪声放大器(Low Noise Amplifier, LNA)。为了在较宽的频带内实现输入阻抗匹配，本文的电路最终采用了共栅-共栅结构；同时运用差分结构增强电路抗干扰能力；为了减小晶体管带来的沟道热噪声，本文使用了双电容交叉耦合结构；用有源电阻代替实际电阻，减小电阻上的压降；采用电流复用技术降低电路功耗。

本文介绍了课题的研究背景、国内外研究现状，并且给出了重要的理论依据，对不同电路结构进行比较分析后介绍了宽带低噪声放大器的具体设计过程，最后使用Cadence软件对电路进行前仿真，并根据仿真结果对电路进行优化。在TT, 27℃条件下，本文设计的低噪声放大器可以在工作频带(0.2~2.5GHz)内，核心工作电路实现小于3mW的功耗，且输入匹配S₁₁小于-10dB，电压增益约为16.82~17.52dB，噪声系数（不加缓冲器）约为2.77~2.89dB，在频率1GHz处，输入1dB压缩点约为-9.14dBm，满足设计指标要求。

关键词：低噪声放大器，CMOS，电容交叉耦合，共栅结构，电流复用技术

ABSTRACT

In recent years, broadband technology with high-rate data transmission capabilities has attracted attention. Nowadays, the development of wireless communication technology is growing rapidly, the requirements for bandwidth and gain of information transmission are increasing. Therefore, there is an urgent need for higher performance wireless communication systems. Low-noise amplifiers are an important part of the energy consumption of receiver modules in wireless communication systems and therefore have a significant impact on receiver performance. This requires designing a low noise amplifier with higher bandwidth, higher gain, lower noise, and better stability. Therefore, the research of broadband low-power low-noise amplifier has good application value and prospect.

Based on TSMC 40nm CMOS technology, this paper designs a low-power Low Noise Amplifier (LNA) with an operating frequency of 0.2~2.5GHz. After comparing the four basic topologies of the low noise amplifier, the circuit finally adopts a double-capacitor cross-coupling common-gate to common-gate structure to achieve wideband input matching and reduce channel thermal noise. Using differential structure to enhance the anti-interference ability of the circuit; replacing the actual resistor with an active resistor to reduce the voltage drop across the resistor; this circuit uses current multiplexing technique to reduce circuit power consumption.

This paper introduces the research background of the subject, the research status at home and abroad, and gives an important theoretical basis. After comparing and analyzing different circuit structures, the specific design process of the broadband low noise amplifier is introduced. Finally, the circuit is pre-simulated using Cadence software, and the circuit is optimized according to the simulation results. Under the condition of TT, 27 °C, the low noise amplifier designed in this paper can realize the power consumption of the core working circuit less than 3mW in the working frequency band (0.2~2.5GHz); the input matching S₁₁ is less than -10dB; the voltage gain is about 16.82~17.52dB; the noise figure (without buffer circuit) is about 2.77~2.89dB; at the frequency 1GHz, the input 1dB compression point is approximately -9.14dBm, reaching the design index requirements.

KEY WORDS: LNA, CMOS, Capacitance cross-coupling, Common-gate structure, Current reuse technology

目 录

第一章 绪论 1

1.1研究背景 1

1.2国内外研究现状 1

1.2.1综述 1

1.2.2国外研究现状 1

1.2.3国内研究现状 3

1.3研究内容及指标 4

1.4论文结构 4

第二章 宽带低噪声放大器设计理论基础 6

2.1低噪声放大器的性能参数 6

2.1.1 输入输出匹配 6

2.1.2噪声系数 6

2.1.3电压增益 7

2.1.4线性度 7

2.1.5稳定性 8

2.2宽带低噪声放大器结构 9

2.2.1分布式放大器结构 9

2.2.2输入并联电阻结构 10

2.2.3电阻负反馈结构 10

2.2.4共栅结构 11

2.3 本章小结 11

第三章 宽带低噪声放大器设计 13

3.1 LNA电路结构设计 13

3.1.1电路结构选择 13

3.1.2跨导增强技术 13

3.2噪声优化 15

3.2.1电容交叉耦合技术 15

3.2.2双电容交叉耦合技术 16

3.3负载的选择 17

3.4输入输出匹配设计 17

3.4.1输入匹配设计 17

3.4.2缓冲器设计 18

3.5电流复用技术 19

3.6本章小结 19

第四章 宽带低噪声放大器仿真 21

4.1仿真平台 21

4.2电路原理图 21

4.3仿真结果 21

4.3.1输入匹配(dB) 22

4.3.2电压增益(dB) 22

4.3.3噪声系数(dB) 23

4.3.4输入1dB压缩点(dBm) 23

4.3.5工作电流(mA) 23

4.3.6稳定系数 24

4.4温度和工艺角仿真 26

4.5针对温度仿真的改进 28

4.5.1问题分析 28

4.5.2改进方案 28

4.6针对噪声系数仿真的改进 28

4.6.1问题分析 28

4.6.2改进方案 28

4.7本章小结 29

第五章 总结与展望 31

5.1总结 31

5.2展望 31

参考文献 33

致 谢 35

附 录 36

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