射频接收机中频率控制模块设计

论文总字数：23213字

摘 要

随着现代通信需求的迅猛增长，通信系统复杂度逐年提升，VCO带宽增大，控制位变得日益复杂，VCO被划分成了更多的子频带，粗调锁定时间在锁相环锁定时间中所占比重越来越大，对射频收发芯片的要求越来越高，传统的频率控制方法已无法满足未来通信系统的要求。

作为芯片中的重要组成部分，频率合成器提供了稳定精确的本振频率，它的性能对于整个通信系统的正常工作产生了重要的影响。随着现代通信技术日趋成熟，对于频率合成器锁定范围的要求也随之提高。采用开关电容阵列是一种较为常见的应对方式，外部的输入信号可以控制开关电容阵列来改变压控振荡器谐振腔内的电容值，继而改变LC-VCO频率带，以此可以实现扩大调谐范围。自动频率校准单元（AFC）的作用是用输出来控制开关电容值，从而使压控振荡器在预期的频率上工作。

本文提出了一种用于L波段宽带接收机的开环AFC单元电路。开环AFC技术中，频率与锁定时间之间是成反比关系的，频率越高，锁定时间就会相应越短。在传统的设计方案中，对经过分频器分频之后的信号进行统计，这相当于是在无形中增加了AFC单元的锁定时间。在频率合成器中，自动频率校准单元（AFC）是锁相环中不能缺少的一个关键部分。锁相环的总锁定时间等于环路锁定时间与自AFC粗调锁定时间之和，因此减少AFC的时间可以提高频率合成器的效率。

本文首先分析了锁相环频率合成器相关的基本工作原理，介绍了包括频率合成技术、锁相环基本结构和锁相环频率合成方式在内的相关问题，并对本文中用到的电荷泵式锁相环的详细性能和结构做出了具体的分析。然后在下一章节中讨论了自动频率校准AFC的电路设计问题，通过对比闭环式自动频率校准和开环式自动频率校准各自的优缺点，结合具体情况和要求提出了文中使用的开环AFC单元设计方案，随后进行了仿真并给出了仿真结果，在第四章中首先介绍了FPGA的理论基础和基本模块，完成了FPGA的设计及测试，随后给出了测试结果，并对结果进行了分析。

关键词：锁相环，快速锁定，频率合成器，自动频率校准单元

Abstract

With the rapid growth of modern communication needs, the complexity of communication system is increasing year by year, and as VCO bandwidth increases, control bits are becoming increasingly complex, so the VCO is divided into more sub-bands.Coarse locking time accounts for a even larger proportion in PLL lock time and a higher requirement for RF transceiver chip is needed. Traditional way of frequency control is unable to meet the requirements of the future communication systems.

As an important part of the chip, frequency synthesizer provides stable and precise local frequency and its performance has an important influence on the normal work of the whole communication system. As broadband communication technology matures, frequency synthesizer need to achieve a wider locking range. A common solution to that is as the following. The resonant cavity of voltage-controlled oscillator cavity adopts switching-capacitance array, and by controlling the array the external signal changes capacitance values of resonant cavity, and then changes the LC-VCO frequency band so as to achieve the goal of expanding the tuning range.The function of automatic frequency calibration unit (AFC) is that by taking such a way that output is used to control the capacitance of the switch to make the voltage-controlled oscillator work on the desired frequency.

This paper puts forward a kind of open-loop AFC unit circuit for L-band broadband receiver. In the technology of open-loop AFC, the frequency is inversely proportional to the lock time, and the higher the frequency the shorter the locking time accordingly. In the traditional design scheme, the signal which is gained from frequency divider is used to carry on statistics, which means that it virtually increases the locking time of the AFC unit. In the frequency synthesizer, automatic frequency calibration unit (AFC) is an indispensable part of the phase-locked loop. The lock time of phase-locked loop is equal to the sum of loop lock time and AFC coarse adjustment of locking time, thus the reduction of the time of the AFC can improve the efficiency of the frequency synthesizer.

This paper first analyzes the basic principle of PLL frequency synthesizer, and introduces such related issues as frequency synthesis technology, the basic structure of phase-locked loop, and the Phase-locked loop frequency synthesis method. The specific performance and structure of charge pump phase-locked loop which is being used in this paper is detailed analyzed. Then the problem of circuit design of AFC is discussed in the next section. By comparing the advantages and disadvantages of closed-loop automatic frequency calibration and open-loop automatic frequency calibration and combined with the specific circumstances and requirements, design scheme of open-loop AFC which is used in this paper is put forward.Then simulation is carried out and its results is presented. In the fourth chapter, the basic theory and basic module of FPGA is firstly introduced and the design and test of FPGA are completed. Then the test results are given and they are analyzed as well.

Keywords：Phase-locked loop, fast locking, frequency synthesizer, AFC

目录

摘要 2

Abstract 3

第一章 绪论 6

1.1课题研究背景及意义 6

1.2 AFC单元研究现状 6

1.3 论文组织结构 7

第二章 锁相环频率合成器 8

2.1 频率合成概念 8

2.2 锁相环快速锁定技术 8

2.2.1 锁相环基本理论 9

2.2.2 快速锁定技术的现状 9

2.3锁相环频率合成器 10

2.4 锁相环频率合成器性能指标 10

2.4.1 频率范围 10

2.4.2 频率分辨率 11

2.4.3 频谱纯净度 11

2.4.4 锁定时间 11

2.5 电荷泵式PLL基本模块 11

2.5.1 鉴频鉴相器 11

2.5.2 电荷泵 12

2.5.3 环路滤波器 12

2.5.4 压控振荡器 13

2.5.5 分频器 13

2.6 本章小结 13

第三章 自动频率校准AFC电路设计 15

3.1 AFC应用背景 15

3.2AFC性能指标 15

3.3AFC结构种类 15

3.3.1闭环式频率校准 15

3.3.2 开环式频率校准 16

3.4 AFC电路设计 17

3.4.1 自动频率校准子带搜索算法 17

3.4.2 系统框图 18

3.4.3流程图 19

3.4.4 时序图 20

3.5 自动频率校准的仿真 21

3.6 本章小结 22

第四章 验证及测试 23

4.1 FPGA基本理论 23

4.1.1 FPGA背景及特点 23

4.1.2 FPGA的工作原理 23

4.2 FPGA基本模块 24

4.2.1 可编程输入输出单元（IOB） 24

4.2.2 可配置逻辑块（CLB） 24

4.2.3 数字时钟管理模块（DCM） 25

4.2.4 嵌入式块RAM（BRAM） 25

4.2.5 丰富的布线资源 25

4.2.6 底层内嵌功能单元 25

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