论文总字数:31151字
摘 要
随着电子信息的高速发展,人们对连接模拟域与数字域的ADC提出了越来越高的性能要求,如5G通信,大数据分析等都需要对大量数据进行处理,而在现有条件下,单片ADC的性能难以同时满足人们的高速高精度需要,而时间交织ADC则是解决这一问题的行之有效的办法。但是存在于TIADC系统中的三种主要失配误差会很大程度上影响系统性能,其中失调失配误差与增益失配误差的校准算法已经趋于成熟,而时钟失配的校准依然是亟待解决的问题,本文主要研究时钟失配的校准算法。
本文首先分析了时间交织ADC的基本原理以及时钟失配效应的时间交织ADC模型,在理论层面研究了时钟失配效应的影响,之后总结分析了一些已有时钟失配校准算法,在此基础上,改进了一种基于数字载波调制的时钟失配前台校准算法,本算法将参考信号输入ADC,得到输出信号与本地提供的载波信号混频,通过累加求均值,再进行反三角运算,就可以得到失配误差值,将相较于原算法提供两路载波输入,本文改进算法只对一路载波进行运算,节省了一半的硬件资源。
在MATLAB与ModelSim中,搭建了一个时间交织ADC模型,对算法的有效性进行了验证。软件仿真结果如下:通道数为四,当输入信号频率为229.4678MHz,TIADC采样速率为600MHz,采样精度为10bits,设置时钟失配误差值为[0,0.02,0.035,-0.02]*的条件下,校准后系统的SNDR,SFDR与ENOB分别由26dB,29.7dB与4位提高至57dB,84.1dB与9.2位。
关键词:时间交织ADC,时钟失配,前台校准,数字载波
Abstract
With the rapid development of electronic information, people are demanding higher and higher performance requirements for ADCs connected to analog and digital domains. For example, 5G communication, big data analysis, etc. need to process large amounts of data, while existing conditions The performance of a single-chip ADC is difficult to meet the high-speed and high-precision needs of people at the same time, and time-interleaved ADC is an effective way to solve this problem. However, the three main mismatch errors existing in the TIADC system will greatly affect the system performance. The calibration algorithm for offset mismatch error and gain mismatch error has matured, and the calibration of clock mismatch is still to be solved. The problem of this paper is to study the calibration algorithm for clock mismatch.
In this paper, the basic principle of time-interleaved ADC and the time-interleaved ADC model of clock mismatch effect are analyzed. The influence of clock mismatch effect is studied at the theoretical level. Then some existing clock mismatch calibration algorithms are summarized and analyzed. A clock mismatch foreground calibration algorithm based on digital carrier modulation is improved. The algorithm inputs the reference signal into the ADC to obtain an output signal mixed with the locally provided carrier signal. By accumulating the average value and then performing an inverse trigonometric operation to obtain the mismatch error value. Compared to the original algorithm what provide two carrier inputs, the improved algorithm only operates on one carrier, saving half of the hardware resources.
In MATLAB and ModelSim, a time-interleaved ADC model is built to verify the effectiveness of the algorithm. The software simulation results are as follows: the number of channels is four, when the input signal frequency is 229.4678MHz, the TIADC sampling rate is 600MHz, the sampling accuracy is 10bits, and the condition that the clock mismatch error value is [0, 0.02, 0.035, -0.02] * Ts is set. Next, the SNDR, SFDR and ENOB of the calibrated system are increased from 26dB, 29.7dB and 4 bits to 57dB, 84.1dB and 9.2 bits, respectively.
KEY WORDS: Time-interleaved ADC, Clock Timing Error Effects, foreground calibration, digital carrier
目 录
摘 要 ..................................................................III
Abstract ...................................................................IV
第一章 绪论 1
1.1研究背景与意义 1
1.2国内外研究现状 2
1.3本论文的主要研究内容 3
1.4本论文的组织结构 3
第二章 时间交织ADC的原理及误差分析 5
2.1时间交织ADC工作原理 5
2.2 时间交织ADC系统的主要性能参数 7
2.3 时间交织ADC主要失配误差分析 8
2.3.1 误差模型建立 9
2.3.2 失调失配分析 9
2.3.3 增益失配误差 11
2.3.4 时钟失配误差 13
2.4 本章小结 15
第三章 时间交织ADC时钟失配校准技术概况 16
3.1 单一前置SHA结构 16
3.2 时间交织ADC时钟失配前台校准技术 17
3.2.1 基于锯齿波输入的前台校准算法 17
3.2.2 基于参考模拟信号的前台校准算法 17
3.3时间交织ADC时钟失配后台校准技术 20
3.4 本章小结 21
第四章 基于数字载波调制的时钟失配校准算法 22
4.1 时钟失配校准算法 22
4.2 失调失配、增益失配对算法的影响分析 23
4.3算法的RTL设计 24
4.4 本章小结 25
第五章 仿真与验证 26
5.1不同输入频率对TIADC系统的影响 26
5.2 时钟误差校准仿真以及不同时钟误差对算法的影响 28
5.3 存在失调失配与增益失配对校准算法的影响仿真 32
5.4 RTL仿真 36
5.5 本章小结 38
第六章 总结与展望 39
6.1 论文内容总结 39
6.2 未来工作展望 39
参考文献 ...................................................................41
致 谢 ...................................................................43
第一章 绪论
1.1 研究背景与意义
在如今电子信息行业,数字处理技术在迅猛发展,相比于传统模拟处理技术,其高速、灵活、可靠性高的优点越来越突出,数字集成电路的发展也更加迅猛[1]。但是,自然界中存在的一般而言都是模拟信号,模数转换器(Analog-to-Digital Converter,ADC)就是将难以直接处理模拟信号转化为数字信号,以便进行数字信号处理。通过ADC,就可以将自然的模拟信号变成可以供数字集成电路处理的数字信号,这样就使得传统的模拟数据处理有了一个全新的方向,在这个方向中,模拟数据处理变得简单且高效。随着电子行业发展迅速,ADC的应用范围越来越广泛,对ADC的性能要求也越来越高。
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